A digital logic circuit, generally formed as a cascade of separate logic functions, is a circuit that produces a digital output as a result of some logical operation on its digital inputs. Digital logic circuits are typically implemented on various types of integrated semiconductor chips. One widely known type of integrated chip is the Application Specific Integrated Circuit (ASIC), which is a custom-made integrated chip. Each ASIC is manufactured to implement a specific digital logic circuit.
Programmable chips are another type of integrated chips, but differ from ASICs because of their ability to implement any number of different complex digital logic circuits by configuring the underlying integrated chip. The programmable integrated chips are less costly, usually in a limited volume, than ASICs because a large number of similar integrated chips may be manufactured from a single design, which can later be configured to implement a wide variety of digital logic circuits. For this reason the cost of design and manufacturing is distributed over a large number of integrated chips.
An FPGA is one type of programmable integrated chips. The FPGA can either be permanently programmed by the user, such as in U.S. Pat. No. 4,758,745 by El Gamal, et al., or can be temporarily programmed by the user, as described in U.S. Pat. No. 4,870,302, by Freeman.
Typically, an FPGA consists of an array of modularized logic units and interconnection resources. It is an array of uncommitted gates with uncommitted wiring channels. Each logic unit can be programmed to implement a particular logic function. Various digital circuits may be implemented to execute desired functions by programming a number of logic blocks and interconnecting them using interconnection resources. In other words, to implement a particular circuit function, the circuit is mapped into the array and the wiring channels and appropriate connections are programmed to implement the necessary wiring connections that form the circuit function. A gate array circuit can be programmed to implement virtually any set of functions.
Of utmost importance in designing an FPGA is the topology of the logic units and the interconnection resources since different FPGA architecture provides different performance characteristics. Also, the programming of a gate array and the mapping of a desired functionality onto it depend upon the topology of the gate array. If the logic units of the gate array are high-level blocks, such as counters, parity generators, and the like, then the amount of programming required is limited to the interconnections among these large- or coarse-grain units.
If, on the other hand, the logic units of the gate array are low-level blocks, such as gates, latches, and the like, then the amount of programming is significantly higher, because these smaller, or fine-grain, units need to be interconnected to affect the higher-level functions. In some designs the use of the fine-grain units results in higher circuit densities because the desired functions can be implemented more efficiently with small low-level units rather than with larger high-level units whose high-level functionality is useless in the particular circumstances.
A highly complex logic unit may be able to perform a large number of complex operations, but if a relatively simple operation is desired, much of the functionality and semiconductor real estate will be wasted. At the same time, a logic unit consisting of basic logic gates requires extensive wiring to perform sophisticated operations. In other words, some complex designs cannot be efficiently embodied in a fine-grain gate array because the amount of interconnection required among the low-level units exceeds the capacity of the gate array.
The traditional implementations of the FPGA logic element units have predominantly focused on a single logic element producing a combinatorial function with arithmetic, sequential, and register packing capabilities. With such architecture, and in many applications, many of the capabilities of an FPGA logic element may remain unused. Various architectures have been proposed to optimize the tradeoffs among circuit building blocks, routing efficiency, performance limits, and the like. There is a need for logic units or a cluster of logic units that optimizes flexibility and functionality of the FPGAs.